1. Field of the Invention
The present invention relates to a timing model for an integrated circuit. More specifically, the present invention relates to method for developing an integrated circuit design to meet timing specifications.
2. Description of the Related Art
Digital circuits, no matter how complex, are composed of a set of building blocks. These blocks can be basic gates, memory cells or other structures. But the majority of digital circuits are composed of gates or combinations of gates. Gates are combinations of high-speed electronic switches. Memory cells are composed of basic logic gates. A flip-flop, for example, can be considered as a memory cell. A microprocessor is a central processing unit of a computer or other device using thousands (or millions) of gates, flip-flops and other memory cells.
Sub-micron designs of integrated circuit chips require accurate timing analysis to prevent operational errors. These timing errors create operational errors which prevent a design, or a manufactured chip, from accomplishing its intended purpose. It is known to use available software tools to design an integrated circuit and to model the functions and timing of the signals on the circuit.
It is known to manufacture an integrated circuit using conductors separated by a semi-conductor. Circuits are fabricated on a semiconductor by selectively altering the conductivity of the semiconductor material. Various conductivity levels correspond to elements of a transistor. Transistors, diodes, resistors, and small capacitors are formed on small chips of silicon. Individual components are interconnected by aluminum or gold wiring patterns. Integrated circuits are then mounted on etched circuit boards which are used to assemble electronic systems such as personal computers and other data processing equipment.
It is known to use commercially available software to model certain features of integrated circuits. For example Verilog, originally designed by Gateway Design Automation in 1985, is a hardware description language (HDL) most predominantly used in the United States. Verilog was made available to the public in 1990 and has been adopted as a standard by the Institute of Electrical and Electronic Engineers (IEEE).
Other electronic design automation (EDA) tools are available to simulate logic of a processor. As electronic design tools became more popular, vendors began to provide enhanced functions. EDA tools are now used to drive synthesis, timing, simulation, test and other tools. Other vendors of EDA tools are: Cadence Corporation, Providence, R.I.; Mentor Graphics, Oreg.; Snyopsys, Calif.; and Snytest Technologies, Inc. California. These products are listed as examples only, other manufactures use proprietary tools for the same purpose. Electronic design automation (EDA) tools were originally designed to simulate logic. As electronic design tools became more popular, vendors began to provide enhanced functions. EDA tools are now used to drive synthesis, timing, simulation, test and other tools. Other vendors of EDA tools are: Cadence Corporation, Providence R.I.; Mentor Graphics, Wilsonville, Oreg.; Snyopsys, Mountainview, Calif.; and Snytest Technologies, Inc., Sunnyvale, Calif. These corporations are listed as examples only, other manufactures use proprietary tools for the same purpose. For example the Silicon Ensemble tool provided by Cadence places and routes wires on the integrated circuit driven by timing constraints.
Register transfer level synthesis (sometimes referred to as xe2x80x9cRTL synthesisxe2x80x9d or simply xe2x80x9csynthesisxe2x80x9d), placement and routing are essential steps to transform a formal functional description of a digital circuit into a design which can be manufactured. Currently available software tools can produce a design according to synthesis, placement and routing. Capacitance, resistance and inductance (collectively referred to as electrical parasitics) resident in the blocks and interconnections influence the timing behavior of the integrated circuit being designed. Thus, neither the electrical performance of the circuit nor the timing behavior are specified in the design.
Referring to FIG. 1, the steps shown are directed to design a circuit with the desired electrical performance and within the specified timing parameters (e.g., correct operation at a given clock frequency and manufactured with a specific die size). The design process consists of subsequent design steps A, B, C . . . M. As further discussed below, design step A is exemplified by RTL synthesis. Design step B is exemplified by placement, 120. Design step C is exemplified by routing, 130.
It will be noted that the variable identifier xe2x80x9cMxe2x80x9d is used in FIG. 2 and FIG. 4 to more simply designate the final step in a series of steps. (Similarly, variable identifier xe2x80x9cNxe2x80x9d is used in FIGS. 3B and 5 for the same purpose.) The use of such variable identifiers does not require that each series of elements has the same number of elements as another series delimited by the same variable identifier. Rather, in each instance of use, the variable identified by xe2x80x9cMxe2x80x9d may hold the same or a different value than other instances of the same variable identifier. Similarly, in each instance of use, the variable identified by xe2x80x9cNxe2x80x9d may hold the same or a different value than other instances of the same variable identifier.
Design Step A, RTL synthesis 110, transforms an abstract behavior description of an electronic circuit into a functionally equivalent structural description. The behavior description is represented in design database A, 114. The structural description is represented in design database B, 124. The components from which the structural description is built are selected from a library. This library has been characterized to contain information necessary to perform embedded timing analysis for the electronic circuit. Referring briefly to FIG. 2, the library contains a timing model for each arc of the component, timing model for arc 260. A timing arc denotes the abstract specification of a timing measurement. (An example of a timing measurement is a delay from rising edge at pin Y to a falling edge at pin Z.) The library also contains at least one parasitic estimation model, 295 (described in FIG. 2, below). The purpose of embedded timing analysis is to enable optimization within 110 until the electronic circuit meets the desired timing specification. Referring briefly to FIG. 2, the desired timing specification is represented by timing constraints and exceptions from designer, 250. Slack distribution A, 118, provides a representation of the result of embedded timing analysis.
Design step B, placement 120, specifies a physical location for each component of the electronic circuit on a silicon die, printed circuit board, etc., based on the structural electronic circuit information in design database B, 124. The result of design step B is represented in design database C, 134. Placement also contains embedded timing analysis and optimization. The timing model for arc, 260, is similar as for design step A. However, parasitic estimation model, 295, is different. In design step A, parasitic estimation was based on structural circuit description only, whereas in design step B placement information is available for more accurate parasitic estimation. Slack distribution B, 128, again provides a representation of the result of embedded timing analysis.
Design step C, routing, 130, specifies physical interconnect routes between the individual components, based on the structural electronic circuit information and placement information in design database C, 134. The result of design step C is represented in reference design database, 140. Routing also contains embedded timing analysis and optimization. The timing model for arc, 260, is similar as for design step A and B. However, the parasitic estimation model, 295, is different. The estimation model is more accurate than in design step A and B, because specific route information is available. Specific route information was not available in design step A and B. Slack distribution C, 138, again provides a representation of the result of embedded timing analysis. Slack distribution, 138, again provides a representation of the result of embedded timing analysis.
Reference timing analysis, 142, is performed in order to verify that the electronic circuit meets the desired timing specification, based on reference design database, 140. Timing model for arc, 260, is similar as for design step A, B, and C. However, the parasitic estimation model, 295, is different. Specific route information is available in the reference design database, 140, for all interconnections of the electronic circuit, whereas in design step C, only partial route information was available, as the route were being specified. Therefore, the most accurate parasitic estimation model, also called parasitic extraction model, is chosen for reference timing analysis, 142. Reference slack distribution, 148, again provides a representation of the result of embedded timing analysis.
FIG. 2 shows details on timing analysis. These details are pertinent to embedded timing analysis in design step A, B, C . . . M as well as to reference timing analysis. Design database A, B, C . . . M, 210, contains information about the implementation of the electronic circuit. Depending on the available implementation information, an appropriate parasitic estimation model, 295, is chosen. The parasitic estimation engine, 220, calculates parasitic data, 270, based on design database, 210, and parasitic estimation model, 295. Therefore, the accuracy of the resulting parasitic data, 270, depends on the available implementation information contained in database, 210, and on the inherent accuracy of the parasitic estimation model, 295. The accuracy of the resulting parasitic data, 270, depends also on the calculation capability of the parasitic estimation engine, 220. Delay calculation engine, 280, calculates the delay, i.e., the elapsed time for a signal to travel from the start point to the end point of a timing arc, for each component in the electronic circuit. This calculation is based on design database, 210, parasitic data, 270, and timing model for arc, 260. The accuracy of the resulting timing data for arc, 290, is therefore limited by the accuracy of the parasitic data, 270. Timing analysis engine, 230, combines timing data for arc, 290, along each path as defined by the structure of the electronic circuit given in design database, 210. Timing analysis engine, 230, compares the combination of timing data for arc, 290, against timing constraints and exceptions from designer, 250, in order to check whether the desired timing is met. The result is represented in slack distribution, 240.
Timing closure is the agreement between timing results in design steps X (X=A,B,C . . . M) and the result of reference timing analysis, which is represented by correlation between the slack distributions resulting from embedded timing analyses in design steps X and the slack distribution resulting from reference timing analysis.
The following conditions are necessary, but not sufficient, to achieve timing closure: similarity between the timing models for arc (260 in FIG. 2); similarity between the delay calculation engines (280 in FIG. 2); similarity between the timing analysis engines (230 in FIG. 2), compatibility between timing constraints and exceptions from designer (250 in FIG. 2). These conditions can be satisfied by choosing and qualifying appropriate software tools for design steps X. For example: Design step A can be performed by the Design Compiler tool from Synopsys or by the BuildGates tool from Cadence; and design step B can be performed by the Qplace tool from Cadence; and design step C can be performed by the Wroute tool from Cadence or by the Apollo tool from Avant!. Alternatively, a combination of design step A and design step B can be performed by the Physical Compiler tool from Synopsys, or the PKS tool from Cadence, etc.
However, estimating the parasitics for each wire is only one of the problems which arise during attempts to achieve timing closure in the design of an integrated circuit. In the early design phase each wire has many degrees of freedom. Therefore any circuit can be designed in several alternate paths. Each path has different electrical parasitics. Therefore, only a lumped capacitance is typically estimated for each wire. Using a lumped capacitance allows a designer to attempt to match the total distributed resistances, inductances and capacitances (collectively known as xe2x80x9cRLCsxe2x80x9d) on a wire. But even if the total RLCs match, the timing would not match, since the effect of distribution of the components is neglected. Another problem is the lack of one-to-one correspondence of logical and physical wires. A logical wire may be broken into multiple physical wires by inserting buffers. Also, the logic of specific functions may be restructured and therefore not preserved, during the process.
In addition, it is not possible to utilize the timing models in the same manner during each step of the design process. During early design steps the timing models should be dependent upon a single value (xe2x80x9clumpedxe2x80x9d) capacitance. In later design steps the timing models are dependent on distributed RLCs. Calculations methods (sometimes referred to as xe2x80x9ceffective capacitancexe2x80x9d methods) should depend on distributed RLCs. Thus, capacitance calculation methods attempt to match the model using a lumped capacitance with the timing based on distributed RLCs. However, the lumped capacitance does not equal the actual capacitance and depends on local electrical effects. These local electrical effects are different from wire to wire, e.g. drive strength, signal transition time. In addition, wire-to-wire capacitance (also known as a xe2x80x9ccrosstalk effectxe2x80x9d) and simultaneously switching signals also change the timing in a way that cannot be accurately accounted for using xe2x80x9ceffective capacitance.xe2x80x9d
In theory, different timing engines analyzing a design under equivalent constraints should give matching results. However, for the following reasons the results must be verified for each design. Convergent timing arcs on a path may be handled algorithmically different by different engines. Timing exceptions (i.e. exclusion of non-relevant paths from analysis) may be handled differently by different engines, or the user may have made mistakes in specifying the intentionally equivalent timing exceptions in different tool-specific languages. This problem would be solved by using the same timing engine for each design step, but this is often not possible. A unique timing engine is embedded in each design tool. The unique timing engines cannot be exchanged between design tools. (As an analogy, a motor is an integral part of a car and cannot be arbitrarily replaced by a motor designed for a different car.)
Attempts in the related art to drive the design tools towards a common timing target correlate the different factors of influence (e.g., electrical parasitics, timing characterization models, and timing engines) in isolation. In some instances, even with a large number of iterations, the timing correlation cannot be satisfied. When timing correlation is not achieved timing closure is not achieved. As a consequence, the RTL synthesis tool, the placement tool and the routing tool may anticipate a different timing result than the actually achieved timing result. Under design leads to excessive iterations, increasing the cost and delaying the production of the design. In the case of over design, the lack of timing correlation leads to a circuit which is larger, slower or consumes more power than necessary to accomplish the desired function.
A method correlates a timing target for electronic design automation (EDA) design tools by comparing slack distributions. A method of designing an integrated circuit can include designing an integrated circuit by RTL synthesis with embedded timing analysis and optimization and placement of cells with embedded timing analysis and optimization. The method can also include designing an integrated circuit by routing with embedded timing analysis and optimization; performing reference timing analysis; performing reference timing analysis and embedded timing analysis using a parasitic estimation model. The method can also include comparing at least two slack distributions resulting from timing analyses. The method can include calculating and comparing autocorrelation functions of slack distributions. The method can include calculating interreorrelation functions of slack distributions.
An embodiment of the disclosure teaches an integrated circuit designed by the method taught. Another embodiment of the disclosure teaches a computer program product including computer instructions configured to perform the method taught.
The foregoing is a summary and this contains, by necessity, simplifications, generalizations and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting.